VERILOG IN MEDICAL APPLICATIONS

Verilog language has no restrictions on course of development of any application or device. It has become extremely popular language for hardware designer, most important reason is that language is based on C. One of the important application of Verilog is in medical applications. We would be seeing few applications in this article.

Starting with processing of ECG signals, ECG signals are most Electrocardiogram (ECG) is important biomedical signal, which show the electrical activity of the heart. ECG waveform provides the valuable information for detection of abnormal heart diseases. For accurate analysis, ECG signal must be processed to remove the noise signal. Also, various features of ECG must be extracted for diagnosis of cardiac disorders. Thus, ECG signal processing includes two stages: Preprocessing and Feature Extraction. Preprocessing stage removes noise from the raw ECG signal and the feature extraction stage extracts diagnostic information from the ECG signal.

For noise removal we would be seeing most recent technique called Empirical Mode Decomposition (EMD), which is a time frequency analysis method suitable for mainly non linear and non stationary signals like ECG. The basic principle of EMD is to decompose a signal into a finite number of IMFs. According to observation the first IMF we get is high frequency component of signal, which is noise. So for removing noise from ecg signal we don’t have to decompose entire signal we just have to find first IMF and subtract it from original signal.

Algorithms of EMD:

1. Finding all maxima and minima of signal x(t)
2. Taking mean between these anvolope. Xavg(t)
3. Candidate IMF is calculated as d1(t)= x(t)- Xavg(t)

        check if d1(t) is IMF or not. If not then take d1(t) as new signal for iteration and again follow the above steps

4. If dk(t) is IMF then subtract IMF from original signal x(t). Result is called residue.

5. Taking this residue signal again perform above steps to convert them into IMF.

Algorithm Flow Chart is

 Implementing this Algorithm in Verilog

Extraction level: Behavioral

1. Extrema Detection: The first process in EMD is to extract local maxima and local minima points (local extrema points). The extraction method is based on the neighboring points given by

i. Local minima: hj[x]<hj[x−1] and hj[x]<hj[x+1] and hi[x]<hi[x+2] and hi[x]<hi[x-2]

ii. Local maxima: hj[x]>hj[x−1] and hj[x]>hj[x+1] and hi[x]>hi[x+2] and hi[x]>hi[x-2]

2. Envolope Generation: Envelope generation is a very difficult process in EMD process. An appropriate interpolation method must be used to connect the local maxima and local minima points, respectively. Three envelope generation methods are cubic spline interpolation (CSI), Sawtooth interpolation, and Hermite Spline Interpolation. Most preferred is Cubic spline interpolation. Numerical method solution is available of this.

3. Stopping Condition : this is to ensure IMF retains sufficient information from the signal by limiting the Standard Deviation. SD between 0.2 & 0.3 we can stop the process.

As previously mentioned we don’t have too calculate all IMFs just first residue is our noise free ECG signal.  We then move for feature extraction.

Feature Extraction: Depending upon Disease that we are trying to predict features are extracted. We will see arrhythmias detection soo depending on RR peak interval different arrhythmias can be detected.

We Again found local maxima of the signal, then we filter out less amplitude peaks…..what we have is series of R peaks, We can calculate RR peak intervals and depending upon different values of RR peaks we can predict arrhythmias.

We saw one example from signal processing there are several others too.

Several system also have been designed on Image processing to name few.. tonsillitis, tumor detection using log gabor filter, breast cancer detection from thermographic images. Ultrasound image enhancement and many more.

Majority of these examples can easily coded in matlab or Simulink due to availability of readymade function and toolbox, which are not present in while manual HDL coding. Manually coding these algorithms can be slow and prone to errors. There is a toolbox in matlab HDL coder which converts matlab file in Verilog model, but many times functions cannot be converted. Another option is Xilinx System Generator for DSP. Xilinx offers highly optimized library of blocks that  can be simulated within Simulink and then compiled for FPGA implementation.